Watchdog Timer; Vmebus Interrupter - Motorola MVME162FX Programmer's Reference Manual

Watchdog Timer

The watchdog timer has a 4-bit counter, four clock select bits, an
enable bit, a local reset enable bit, a SYSRESET enable bit, a board
fail enable bit, counter reset bit, WDTO status bit, and WDTO status
reset bit.
When enabled, the counter increments at a rate determined by the
clock select bits. If the counter is not reset by software, the counter
reaches its terminal count. When this occurs, the WDTO status bit
is set; and if the local or SYSRESET function is enabled, the selected
reset is generated; if the board fail function is enabled, the board fail
signal is generated.

VMEbus Interrupter

The interrupter provides all the signals necessary to allow software
to request interrupt service from a VMEbus interrupt handler. The
chip connects to all signals that a VMEbus interrupter is required to
drive and monitor.
Requiring no external jumpers, the chip provides the means for
software to program the interrupter to request an interrupt on any
one of the seven interrupt request lines. In addition, the chip
controls the propagation of the acknowledge on the IACK
daisy-chain.
The interrupter operates in the release-on-acknowledge (ROAK)
mode. An 8-bit control register provides software with the means
to dynamically program the status/ID information. Upon reset,
this register is initialized to a status/ID of $0F (the uninitialized
vector in the 68K-based environment).
The VMEbus interrupter has an additional feature not defined in
the VMEbus specification. The VMEchip2 supports a broadcast
mode on the IRQ1 signal line. When this feature is used, the normal
IRQ1 interrupt to the local bus interrupter should be disabled and
the edge-sensitive IRQ1 interrupt to the local bus interrupter
Functional Blocks
2-17
2