Local Bus To Vmebus Requester - Motorola MVME162FX Programmer's Reference Manual

VMEchip2
2

Local Bus to VMEbus Requester

2-8
VMEbus. If the data transfer does not begin before the timer times
out, the timer drives the local bus error signal, and sets the
appropriate status bit in the Local Control and Status Register
(LCSR). Using control bits in the LCSR, the timer can be disabled,
or it can be enabled to drive the local bus error signal after 64 µs, 1
ms, or 32 ms.
The VMEchip2 includes a software-controlled VMEbus write post
timer, and it starts ticking when a data transfer to the VMEbus is
write posted. The timer stops ticking once the chip has started the
data transfer on the VMEbus. If this does not happen before the
timer times out, the chip aborts the write posted cycle and send an
interrupt to the local bus interrupter. If the write post bus error
interrupt is enabled in the local bus interrupter, the local processor
is interrupted to indicate a write post time-out has occurred. The
write post timer has the same timing as the VMEbus access timer.
The requester provides all the signals necessary to allow the local
bus to VMEbus master to request and be granted use of the
VMEbus. The chip connects to all signals that a VMEbus requester
is required to drive and monitor.
Requiring no external jumpers, the chip provides the means for
software to program the requester to request the bus on any one of
the four bus request levels, automatically establishing the bus grant
daisy-chains for the three inactive levels.
The requester requests the bus if any of the following conditions
occur:
1. The local bus master initiates either a data transfer cycle or an
interrupt acknowledge cycle to the VMEbus.
2. The chip is requested to acquire control of the VMEbus as
signaled by the DWB input signal pin.
3. The chip is requested to acquire control of the VMEbus as
signaled by the DWB control bit in the LCSR.