Vmebus System Controller; Arbiter - Motorola MVME162FX Programmer's Reference Manual

VMEchip2
2

VMEbus System Controller

Arbiter

2-18
should be enabled. All boards in the system which are not
participating in the broadcast interrupt function should not drive or
respond to any signals on the IRQ1 signal line.
There are two ways to broadcast an IRQ1 interrupt. The VMEbus
interrupter in the VMEchip2 may be programmed to generate a
level one interrupt. This interrupt must be cleared using the
interrupt clear bit in the control register because the interrupt is
never acknowledged on the VMEbus. The VMEchip2 allows the
output of one of the tick timers to be connected to the IRQ1
interrupt signal line on the VMEbus. When this function is enabled,
a pulse appears on the IRQ1 signal line at the programmed
interrupt rate of the tick timer.
With the exception of the optional SERCLK Driver and the Power
Monitor, the chip includes all the functions that a VMEbus System
Controller must provide. The System Controller is
enabled/disabled with the aid of an external jumper (the only
jumper required in a VMEchip2 based VMEbus interface).
The arbitration algorithm used by the chip arbiter is selected by
software. All three arbitration modes defined in the VMEbus
Specification are supported: Priority (PRI), Round-Robin-Select
(RRS), as well as Single (SGL). When operating in the PRI mode, the
arbiter asserts the BCLR line whenever it detects a request for the
bus whose level is higher that the one being serviced.
The chip includes an arbitration timer, preventing a bus lockup
when no requester assumes control of the bus after the arbiter has
issued a grant. Using a control bit, this timer can be enabled or
disabled. When enabled, it assumes control of the bus by driving
the BBSY signal after 256 µsecs, releasing it after satisfying the
requirements of the VMEbus specification, and then re-arbitrating
any pending bus requests.