Programming The Tick And Watchdog Timers; Vmebus Arbiter Time-Out Control Register - Motorola MVME162FX Programmer's Reference Manual

VMEchip2
2

Programming the Tick and Watchdog Timers

VMEbus Arbiter Time-out Control Register

ADR/SIZ
BIT
NAME
OPER
RESET
2-66
When this bit is set, the DMAC received a TEA and
DLBE
additional status was not provided. This bit is
cleared when the DMAC is enabled.
MLTO When this bit is set, the MPU received a TEA and the
status indicated a local bus time-out. This bit is
cleared by a writing a one to the MCLR bit in this
register.
The VMEchip2 has two 32-bit tick timers and one watchdog timer.
This section provides addresses and bit level descriptions of the
prescaler, tick timer, watchdog timer registers and various other
timer registers.
$FFF4004C (8 bits [1 used] of 32)
31 30 29
This register controls the VMEbus arbiter time-out timer.
ARBTO When this bit is high, the VMEbus grant time-out
timer is enabled. When this bit is low, the VMEbus
grant timer is disabled. When the timer is enabled
and the arbiter does not receive a BBSY signal within
256 µs after a grant is issued, the arbiter asserts BBSY
and removes the grant. The arbiter then rearbitrates
any pending requests.
28 27 26 25 24
ARBTO
R/W
0 PS