Dram Control Register - Motorola MVME172 Programmer's Reference Manual

DRAM Control Register

This register controls the parity checking mode and DRAM enable for
non-ECC applications.
ADR/SIZ
BIT
31
NAME
OPER R/W
RESET
0
RAMEN
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signal is sent to the local bus. Note that the Version
Register bit V1 must be set to a 1 to enable the MC2 chip
access timer (i.e., it must be a "No VMEbus Interface"
option).
0
1
2
3
$FFF42048 (8 bits)
30 29 28
R/W R/W R/W
0 0 0
This bit enables the access of the DRAM. The DRAM
should be enabled after the DRAM Space Base Address
Register is enabled and the ROM0 bit has been cleared.
The DRAM Space Base Address Register is located at
$FFF42020 bits 31 - 16 and the ROM0 bit is located at
$FFF42040 bit 20.
8 s
64 s
256 s
The timer is disabled.
27 26
WWP PARINT PAREN
R/W R/W
0 PL 0 PL
Programming Model
25 24
RAMEN
R/W R/W
0 PL 0 PL
3-45
3