Sram Memory Controller; Dram Memory Controller; Table 3-1. Dram Performance - Motorola MVME162FX Programmer's Reference Manual

MC2 Chip

SRAM Memory Controller

3

DRAM Memory Controller

Clock Budget
3-6
The SRAM base address and size are programmable. The SRAM
controller is designed to operate with 100 ns devices. The size of the
SRAM is initialized in the DRAM/SRAM Options Register when
the MVME162FX is reset. SRAM performance at 25MHz is 5,3,3,3
for read and write cycle. SRAM performance at 32MHz is 6,4,4,4 for
read cycles and 6,3,3,3 for write cycles.
The DRAM base address, DRAM array size, and DRAM device size
are programmable. The DRAM controller assumes an interleaved
architecture if the DRAM size requires eight physical devices. (That
is, there are two memory configurations which allow interleaved
DRAM architecture: when memory array size is 4MB and DRAM
technology is 4-Mbits per device; and when memory array size is
16MB and DRAM technology is 16-Mbits per device.)
Parity checking and parity exception action is also programmable.
The DRAM array size and DRAM device size are initialized in the
DRAM/SRAM Options Register.
The present MVME162FX models do not contain parity
Note
DRAM.

Table 3-1. DRAM Performance

4,2,2,2 Non-interleaved, read, 25MHz, without TEA on parity error
4,1,1,1 Interleaved, read, 25MHz, without TEA on parity error
5,3,3,3 Non-interleaved, read, 25MHz, with TEA on parity error
5,2,2,2 Interleaved, read, 25MHz, with TEA on parity error
3,2,2,2 Write, 25MHz
5,3,3,3 Non-interleaved, read, 32MHz, without TEA on parity error
Operating Conditions