Access And Watchdog Time Base Select Register - Motorola MVME162FX Programmer's Reference Manual

MC2 Chip

Access and Watchdog Time Base Select Register

3
ADR/SIZ
BIT
NAME
OPER
RESET
3-46
The watchdog timer control logic in the MC2 chip is used with the
ÒNo VMEbus InterfaceÓ option. This function is duplicated at the
same bit locations in the VMEchip2 at location $FFF4004C. It is
permissible to enable the watchdog timer in both the VMEchip2
and the MC2 chip.
15 14 13
R/W
0
WDTO These bits define the watchdog time-out period:
Bit Encoding
0
1
2
3
4
5
6
7
These bits define the local bus time-out value. The
LBTO
timer begins timing when TS is asserted on the local
bus. If TA or TAE is not asserted before the timer
times out, a TEA signal is sent to the local bus. Note
that the Version Register bit V1 must be set to a 1 to
enable the MC2 chip access timer (i.e., it must be a
ÒNo VMEbus InterfaceÓ option).
0
1
2
3
$FFF42044 (8 bits)
12 11
LBTO
R/W
0 PL
Time-out Bit Encoding
512 µs
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
8 µs
64 µs
256 µs
The timer is disabled.
10 9 8
WDTO
R/W
0 PL
Time-out
8 128 ms
9 256 ms
10 512 ms
11 1 s
12 4 s
13 16 s
14 32 s
15 64 s