Interrupt Vector Base Register - Motorola MVME162FX Programmer's Reference Manual

MC2 Chip

Interrupt Vector Base Register

3
ADR/SIZ
BIT
NAME
OPER
RESET
3-14
The interrupt vector base register is an 8-bit read/write register that
is used to supply the vector to the MC68xx040 during interrupt
acknowledge cycles. Only the most significant four bits are used.
The least significant four bits encode the interrupt source during
the acknowledge cycle. The exception to this is that after reset
occurs, the interrupt vector passed is $0f, which remains in effect
until a write is generated to the vector base register. A normal read
access to the vector base register yields the value $0f if the read
happens before it has been initialized. A normal read access yields
all 0s on bits 0-3 and the value that was written on bits 4-7 if the read
happens after the register has been initialized.
7 6
IV7 IV6 IV5
R/W R/W R/W
0 PL 0 PL 0 PL
The encoding for the interrupt sources is shown in the next table,
where IV3-IV0 refer to bits 3-0 of the vector passed during the IACK
cycle:
The priority referenced in the following table is established in the
MC2 chip logic by implementing a daisy chain request/grant
network. There is a similar request/grant daisy chain at the board
level. At the board level, the MC2 chip is wired to have the highest
priority followed by the IndustryPack interface ASIC (IP2 chip) and
then the VMEchip2 ASIC.
$FFF42000 (8 bits)
5 4 3
IV4 IV3
R/W R
0 PL 1 PL
2 1 0
IV2 IV1 IV0
R R R
1 PL 1 PL 1 PL