Dram Parity Error Interrupt Control Register - Motorola MVME162FX Programmer's Reference Manual

DRAM Parity Error Interrupt Control Register

The DRAM Parity Error Interrupt Control Register controls the
interrupt logic for parity error interrupts. In the MVME162FX, the
parity control and interrupt logic is contained in the DRAM Parity
Error Interrupt Control Register and the DRAM Control Register
located at $FFF4201C and $FFF42048 respectively.
ADR/SIZ
31
BIT
NAME
OPER R
RESET 0
IL2-IL0
ICLR
Note
IEN
INT
$FFF4201C (8 bits)
30 29 28
INT IEN
R R R/W
0 0 PL 0 PL
These three bits select the interrupt level for the
DRAM parity error detection. Level 0 does not
generate an interrupt.
Writing a logic 1 to this bit clears the DRAM parity
error detection interrupt. This clears the INT bit in
this register. This bit is always read as zero.
Do not set the IEN bit unless parity is supported by the
DRAM mezzanine. The present MVME162FX models
do not contain parity DRAM.
This bit set to a one enables the parity error
interrupt. If this bit is set to a one, and the PAREN
and PARINT bits are set to 01 or 11, and a parity
error occurs, an interrupt is generated at the level
programmed in the IL2-IL0 bits. The PAREN and
PARINT bits are located at $FFF42048 at bit 26 and
25.
When this bit is high, a interrupt is being generated
due to a DRAM parity error. The interrupt is at the
level programmed in IL2-IL0.
Programming Model
27 26 25
ICLR IL2 IL1
C R/W R/W
0 PL 0 PL 0 PL
3
24
IL0
R/W
0 PL
3-23