Tick Timers; Watchdog Timer - Motorola MVME162FX Programmer's Reference Manual

MC2 Chip

Tick Timers

3

Watchdog Timer

3-8
The MC2 chip implements four 32-bit tick timers. These timers are
identical to the timers in the VMEchip2. The timers run on a 1MHz
clock which is derived from the processor clock by a prescaler.
Each timer has a 32-bit counter, a 32-bit compare register, and a
clear-on-compare enable bit. The counter is readable and writable
at any time. These timers can be used to generate interrupts at
various rates or the counters can be read at various times for
interval timing. There are two modes of operation for these timers:
free-running and clear-on-compare.
In the free-running mode, the timers have a resolution of 1 µs and
roll over after the count reaches the maximum value $FFFFFFFF.
The terminal count period for the timers is 71.6 minutes.
When the counter is enabled in the clear-on-compare mode, it
increments every 1 µs until the counter value matches the value in
the compare register. When a match occurs, the counter is cleared.
When a match occurs, in either mode, an interrupt is sent to the
local bus interrupter and the overflow counter is incremented. An
interrupt to the local bus is only generated if the tick timer interrupt
is enabled by the local bus interrupter. The overflow counter can be
cleared by writing a one to the overflow clear bit.
A watchdog timer function is provided in the VMEchip2 and the
MC2 chip. The watchdog timer implemented in the MC2 chip is
used when the ÒNo VMEbus InterfaceÓ option is enabled. When the
watchdog timer is enabled, it must be reset by software within the
programmed time or it times out. The watchdog timer can be
programmed to generate a board level reset signal or board fail
signal if it times out. Note that, unlike the VMEchip2, the MC2 chip
timer cannot generate a system reset because it is not connected to
the VMEbus.