Mpu Status And Dma Interrupt Count Register - Motorola MVME162FX Programmer's Reference Manual

VMEchip2

MPU Status and DMA Interrupt Count Register

2
ADR/SIZ
BIT
NAME
OPER
RESET
2-64
15 14 13
DMAIC
R
0 PS
This is the MPU status register and DMAC interrupt counter.
MLOB When this bit is set, the MPU received a TEA and the
status indicated off-board. This bit is cleared by
writing a one to the MCLR bit in this register.
MLPE When this bit is set, the MPU received a TEA and the
status indicated a parity error during a DRAM data
transfer. This bit is cleared by writing a one to the
MCLR bit in this register. This bit is not defined for
MVME162FX implementation.
When this bit is set, the MPU received a TEA and
MLBE
additional status was not provided. This bit is
cleared by writing a one to the MCLR bit in this
register.
MCLR Writing a one to this bit clears the MPU status bits 7,
8, 9 and 10 (MLTO, MLOB, MLPE, and MLBE) in this
register.
DMAIC The DMAC interrupt counter is incremented when
an interrupt is sent to the local bus interrupter. The
value in this counter indicates the number of
commands processed when the DMAC is operated
in the command chaining mode. If interrupt count
exceeds 15, the counter rolls over. This counter
operates regardless of whether the DMAC
interrupts are enabled. This counter is cleared when
the DMAC is enabled.
$FFF40048 (8 bits of 32)
12 11
MCLR
C
0 PS
10 9 8
MLBE MLPE MLOB
R R R
0 PS 0 PS 0 PS