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MC2 Chip
Access and Watchdog Time Base Select Register
3
ADR/SIZ
BIT
NAME
OPER
RESET
3-44
The watchdog timer control logic in the MC2 chip is used with the "No
VMEbus Interface" option. This function is duplicated at the same bit
locations in the VMEchip2 at location $FFF4004C. It is permissible to
enable the watchdog timer in both the VMEchip2 and the MC2 chip.
15
14
13
R/W
0
WDTO
These bits define the watchdog time-out period:
Bit
Encoding
0
1
2
3
4
5
6
7
LBTO
These bits define the local bus time-out value. The timer
begins timing when TS is asserted on the local bus. If TA
or TEA is not asserted before the timer times out, a TEA
$FFF42044 (8 bits)
12
11
LBTO
R/W
0PL
Time-out
s
512
s
1 m
s
2 m
s
4 m
s
8 m
s
6 m
s
32 m
s
64 m
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10
9
8
WDTO
R/W
0 PL
Bit
Time-out
Encoding
s
8
128 m
s
9
256 m
0
s
1
512 m
1
s
1
1
2
s
1
4
3
s
1
16
4
s
1
32
5
1
64 s
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