Sram Space Size Register; Table 3-7. Sram Size Control Bit Encoding - Motorola MVME172 Programmer's Reference Manual

SRAM Space Size Register

ADR/SIZ
BIT
15
NAME
OPER R
RESET
0 PL
SEN
SZ1-SZ0
Note
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$FFF42024 (8 bits)
14 13 12
SRAM ENABLE must be set to a one before the SRAM
can be accessed.
The size bits configure the SRAM decoder for a particular
memory size. The following table defines their use. Note
that the table specifies the allowed bit combinations for
SZ1 - SZ0. Any other combinations generate
unpredictable results.
SZ1 - SZ0 are set equal to the SZ1 - SZ0 bits of the
DRAM/SRAM Options Register. SZ1 - SZ0 are
programmable to facilitate diagnostic software.

Table 3-7. SRAM Size Control Bit Encoding

SZ1 - SZ0
$0
$1
$2
$3
For an MVME172 with 128 KB of SRAM, the software must
program SZ1-SZ0 = $1 (512 KB). Therefore, the SRAM
contents will repeat in the memory map.
Programming Model
11 10
SEN
Memory Size
Reserved (do not use)
512 KB (or 128 KB)
1 MB
2 MB
9 8
SZ1 SZ0
3-29
3