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WDCS
SRST
Tick Timer 2 Control Register
ADR/SIZ
BIT
15
NAME
OPER
RESET
EN
COC
COVF
OVF
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When this bit is set high, the watchdog time-out status bit
(WDTO bit in this register) is cleared.
When this bit is set high, a SYSRESET signal is generated
on the VMEbus. SYSRESET resets the VMEchip2 and
clears this bit.
$FFF40060 (8 bits [7 used] of 32)
14
13
12
OVF
R
0 PS
When this bit is high, the counter increments. When this
bit is low, the counter does not increment.
When this bit is high, the counter is reset to zero when it
compares with the compare register. When this bit is low,
the counter is not reset.
The overflow counter is cleared when a one is written to
this bit.
These bits are the output of the overflow counter. The
overflow counter is incremented each time the tick timer
sends an interrupt to the local bus interrupter. The
overflow counter can be cleared by writing a one to the
COVF bit.
LCSR Programming Model
11
10
9
COVF
COC
C
R/W
0 PS
0 PS
2
8
EN
R/W
0 PS
2-73
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