Interrupt Vector Base Register - Motorola MVME172 Programmer's Reference Manual

SCCIT<1:0>These bits define the IACK daisy chain time for the SCC
These bits must be initialized to 01 for the MVME172 boards
!
because they contain two Z85230 devices.
Caution

Interrupt Vector Base Register

The interrupt vector base register is an 8-bit read/write register that is used
to supply the vector to the MC68xx060 during interrupt acknowledge
cycles. Only the most significant four bits are used. The least significant
four bits encode the interrupt source during the acknowledge cycle.
The exception to this is that after reset occurs, the interrupt vector passed
is $0f, which remains in effect until a write is generated to the vector base
register.
A normal read access to the vector base register yields the value $0f if the
read happens before it has been initialized. A normal read access yields all
0s on bits 0-3 and the value that was written on bits 4-7 if the read happens
after the register has been initialized.
ADR/SIZ
BIT
7
NAME
IV7
OPER R/W
RESET
0 PL
http://www.mcg.mot.com/literature
chips. They must be set based on the number of SCC
devices.
SCCIT<1:0>
00
01
10
11
$FFF42000 (8 bits)
6 5 4
IV6 IV5 IV4
R/W R/W R/W
0 PL 0 PL 0 PL
Programming Model
Number of Z85230s
1
2
3
4
3 2
IV3 IV2
R R
1 PL 1 PL
1 0
IV1 IV0
R R
1 PL 1 PL
3-13
3