No-Vmebus-Interface Option; Memory Options; Dram - Motorola MVME162P2 Series Installation And Use Manual

The MVME162P2 local bus slaves that support the snoop/caching mode
are defined in the "Local Bus Memory Map" section of the MVME1X2P2
VME Embedded Controller Programmer's Reference Guide.
Note

No-VMEbus-Interface Option

In support of possible future configurations in which the MVME162P2
might be offered as an embedded controller without the VMEbus interface,
certain logic in the VMEchip2 has been duplicated in the Petra chip. (For
the location of the overlapping logic, refer to Chapter 1 in the
MVME1X2P2 VME Embedded Controller Programmer's Reference
Guide.) As long as the VMEchip2 ASIC is present, the redundant logic is
inhibited in the Petra chip. The enabling signals for these functions are
controlled by software and Petra chip hardware initialization.

Memory Options

The following memory options are available on the different versions of
MVME162P2 boards.

DRAM

MVME162P2 boards are built with 16MB or 32MB shared DRAM
(SDRAM). Depending on build options chosen at the time of manufacture,
various versions of the MVME162P2 have the SDRAM configured to
model 1MB, 4MB, 8MB, or 16MB of parity-protected DRAM or 4MB,
8MB, 16MB, or 32MB of ECC-protected DRAM.
http://www.motorola.com/computer/literature
As outlined in Table 1-9, the snoop capabilities of the
MC68xx040 processor differ from those of the MC68xx060 used
on MVME172P2 series boards. Application software must take
these differences into account.
Functional Description
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