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VMEchip2
2
DMAC Status Register
ADR/SIZ
BIT
NAME
OPER
RESET
2-64
DMAIC
The DMAC interrupt counter is incremented when an
interrupt is sent to the local bus interrupter. The value in
this counter indicates the number of commands processed
when the DMAC is operated in the command chaining
mode. If interrupt count exceeds 15, the counter rolls over.
This counter operates regardless of whether the DMAC
interrupts are enabled. This counter is cleared when the
DMAC is enabled.
7
6
MLTO
DLBE
DLPE
R
R
0 PS
0 PS
0 PS
This is the DMAC status register.
DONE
This bit is set when the DMAC has finished executing
commands and there were no errors or the DMAC has
finished executing command because the halt bit was set.
This bit is cleared when the DMAC is enabled.
VME
When this bit is set, the DMAC received a VMEbus
BERR during a data transfer. This bit is cleared when the
DMAC is enabled.
TBL
When this bit is set, the DMAC received an error on the
local bus while it was reading commands from the
command packet. Additional information is provided in
bits 3 - 6 (DLTO, DLOB, DLPE, and DLBE). This bit is
cleared when the DMAC is enabled.
DLTO
When this bit is set, the DMAC received a TEA and the
status indicated a local bus time-out. This bit is cleared
when the DMAC is enabled.
$FFF40048 (8 bits of 32)
5
4
3
DLOB
DLTO
R
R
R
0 PS
0 PS
Computer Group Literature Center Web Site
2
1
0
TBL
VME
DONE
R
R
R
0 PS
0 PS
0 PS
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