Clocked Serial Interface N (Csin); Features; Configuration - NEC V850ES/SA2 UPD703201 Manual

32-bit single-chip microcontrollers
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12.3 Clocked Serial Interface n (CSIn)

12.3.1 Features

• Transfer rate: Master mode: Maximum 5 Mbps (when internal system clock operates at 10 MHz)
Slave mode:
• Half-duplex communications
• Master mode and slave mode can be selected
• Transmission data length: 8 bits
• Transfer data direction can be switched between MSB first and LSB first
• Eight clock signals can be selected (7 master clocks and 1 slave clock)
• 3-wire method
• SOn:
Serial data output
• SIn:
Serial data input
• SCKn: Serial clock input/output
• Interrupt sources: 1 type
• Transmission/reception completion interrupt (INTCSIn)
• Transmission/reception mode or reception-only mode can be specified
• On-chip transmit buffer (SOTBn)
Remark
n = 0 to 3 (V850ES/SA2)
n = 0 to 4 (V850ES/SA3)

12.3.2 Configuration

CSIn is controlled by the clocked serial interface mode register (CSIMn). Transmit/receive data can be written to or
read from the SIOn register.
(1) Clocked serial interface mode register n (CSIMn)
The CSIMn register is an 8-bit register for specifying the operation of CSIn.
(2) Clocked serial interface clock selection register n (CSICn)
The CSICn register is an 8-bit register for controlling the transmit operation of CSIn.
(3) Serial I/O shift register n (SIOn)
The SIOn register is an 8-bit register for converting between serial data and parallel data. SIOn is used for
both transmission and reception.
Data is shifted in (reception) or shifted out (transmission) beginning at either the MSB side or the LSB side.
Actual transmit/receive operations are controlled by reading or writing SIOn.
(4) Clocked serial interface transmit buffer register n (SOTBn)
The SOTBn register is an 8-bit buffer register for storing transmit data.
(5) Selector
The selector selects the serial clock to be used.
(6) Serial clock controller
The serial clock controller controls the supply of serial clocks to the shift register. When an internal clock is
used, it also controls the clocks that are output to the SCKn pin.
330
CHAPTER 12 SERIAL INTERFACE FUNCTION
Maximum 5 Mbps
Preliminary User's Manual U15905EJ1V0UD

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