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5.6
Wait Function
5.6.1
Programmable wait function
(1) Data wait control register 0 (DWC0)
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus
cycle that is executed for each CS space.
The number of wait states can be programmed by using data wait control register 0 (DWC0). Immediately after
system reset, 7 data wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
always accessed without a wait state. The internal peripheral I/O area is also not subject
to programmable wait, and only wait control from each peripheral function is performed.
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do
not access an external memory area other than the one for this initialization routine until
the initial settings of the DWC0 register are complete. However, external memory areas
whose initial settings are complete may be accessed.
After reset:
DWC0
CSn signal
CSn signal
DWn2
Caution Be sure to clear bits 15, 11, 7, and 3 to 0.
192
CHAPTER 5 BUS CONTROL FUNCTION
7777H
R/W
Address:
15
14
13
0
DW32
DW31
CS3
7
6
5
0
DW12
DW11
CS1
DWn1
DWn0
Number of wait states inserted in CSn space (n = 0 to 3)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Preliminary User's Manual U15905EJ1V0UD
FFFFF484H
12
11
10
DW30
0
DW22
4
3
2
DW10
0
DW02
None
1
2
3
4
5
6
7
9
8
DW21
DW20
CS2
1
0
DW01
DW00
CS0
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