Operation - NEC V850ES/SA2 UPD703201 Manual

14.2.1 Operation

If a non-maskable interrupt is generated by NMI input, the CPU performs the following processing, and transfers
control to the handler routine.
<1> Saves the restored PC to FEPC.
<2> Saves the current PSW to FEPSW.
<3> Writes exception code 0010H to the higher halfword (FECC) of ECR.
<4> Sets the NP and ID bits of the PSW and clears the EP bit.
<5> Sets the handler address (00000010H, 00000020H) corresponding to the non-maskable interrupt to the PC,
and transfers control.
The servicing configuration of a non-maskable interrupt is shown in Figure 14-2.
Figure 14-2. Servicing Configuration of Non-Maskable Interrupt
INTC
acknowledged
CPU processing
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
NMI input
Non-maskable interrupt request
PSW.NP
0
FEPC Restored PC
FEPSW PSW
ECR.FECC 0010H
PSW.NP 1
PSW.EP 0
PSW.ID 1
PC 00000010H,
00000020H
Interrupt servicing
Preliminary User's Manual U15905EJ1V0UD
1
Interrupt request held pending
423