C Interrupt Request (Intiic) - NEC V850ES/SA2 UPD703201 Manual

32-bit single-chip microcontrollers
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2
12.4.5 I

C interrupt request (INTIIC)

The following shows the value of the IIC status register (IICS) at the INTIIC interrupt request generation timing and
at the INTIIC interrupt timing.
(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception)
<1> When WTIM = 0
ST
AD6 to AD0
L1: IICS = 10XXX110B
L2: IICS = 10XXX000B
L3: IICS = 10XXX000B (WTIM = 0)
L4: IICS = 10XXXX00B
∆ 5: IICS = 00000001B
Remark L: Always generated
∆: Generated only when SPIE = 1
X: Don't care
<2> When WTIM = 1
ST
AD6 to AD0
L1: IICS = 10XXX110B
L2: IICS = 10XXX100B
L3: IICS = 10XXXX00B
∆ 4: IICS = 00000001B
Remark L: Always generated
∆: Generated only when SPIE = 1
X: Don't care
CHAPTER 12 SERIAL INTERFACE FUNCTION
RW
AK
D7 to D0
L1
L2
RW
AK
D7 to D0
L1
Preliminary User's Manual U15905EJ1V0UD
SPT = 1
AK
D7 to D0
AK
L3
L4
SPT = 1
AK
D7 to D0
AK
L2
L3
SP
∆5
SP
∆4
367

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