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8.3
Operation
8.3.1
Initializing counter and count-up
<1> When the RESET input signal is asserted (0), the values of RTC control registers 0 and 1 (RTCC0 and
RTCC1) are initialized. Real-time counter clock operation is enabled when RTCAE of the RTCC0 register is
set to 1, and real-time counter count operation is enabled when RTCE of the RTCC1 register is set to 1.
<2> The sub-count register (SUBC) is reset if the real-time count clock operation is stopped when RTCAE is 0.
<3> The real-time counter clock operation is stopped when the CKS bit of the RTCC0 register is selected and
RTCAE is set to 1.
<4> After 3 internal clocks, the values of all the count setting registers are reflected on the corresponding count
registers at all once, and each count register starts counting up.
<5> Each time a count register overflows, the higher count register starts counting up.
<6> At the clock after the one at which the overflow conditions of all the count registers have been satisfied, all the
count registers are cleared to "0". The INTROV signal is asserted active for the duration of one cycle of the
real-time count clock after the week count register (WEEK) overflows.
8.3.2
Rewriting counter
<1> When the RESET input signal is asserted (0), the values of the RTCC0 and RTCC1 registers are initialized.
Real-time counter clock operation is enabled when RTCAE is set to 1, and real-time counter count operation
is enabled when RTCE is set to 1.
<2> Write a value to each count setting register.
<3> The value of all the count setting registers are reflected on the corresponding count registers all at once two
internal clocks after RTCE is set to 1, and the real-time counter starts counting up 3 internal clocks after that.
270
CHAPTER 8 REAL-TIME COUNTER FUNCTION
Preliminary User's Manual U15905EJ1V0UD
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