Control Registers - NEC V850ES/SA2 UPD703201 Manual

7.1.4

Control registers

(1) Timer mode control registers 00 and 10 (TMC00 and TMC10)
The TMCn0 registers control the operation of TMn (n = 0, 1).
These registers can be read or written in 8-bit or 1-bit units.
Be sure to set bits 3 and 2 to 0. If they are set to 1, the operation is not guaranteed.
Cautions 1. The TMCAEn bit cannot be set at the same time as the other bits. The other bits and the
registers of the other TMn units should always be set after the TMCAEn bit has been set.
Also, to use external pins related to the timer function when the 16-bit timer/event counter
is used, be sure to set (1) the TMCAEn bit after setting the external pins to control mode.
2. When conflict occurs between an overflow and a TMCn0 register write, the OVFn bit value
becomes the value written during the TMCn0 register write (n = 0, 1).
After reset:
TMCn0
(n = 0,1)
When TMn has counted up from FFFFH to 0000H, the OVFn bit becomes 1 and an
overflow interrupt request (INTOVFn) is generated at the same time. However, if
TMn is cleared to 0000H after a match at FFFFH when the CCn0 register is set to
compare mode (CMSn0 bit of TMCn1 register = 1) and clearing is enabled for a
match when TMn and CCn0 are compared (CCLRn bit of TMCn1 register = 1), then
TMn is considered to be cleared and the OVFn bit does not become 1. Also, no
INTOVFn interrupt is generated.
The OVFn bit retains the value 1 until 0 is written directly or until an asynchronous
reset is performed because the TMCAEn bit is 0. An interrupt operation due to an
overflow is independent of the OVFn bit, and the interrupt request flag (OVFIFn) for
INTOVFn is not affected even if the OVFn bit is manipulated. If an overflow occurs
while the OVFn bit is being read, the flag value changes, and the change is reflected
when the next read operation occurs.
CHAPTER 7 TIMER/COUNTER FUNCTION
00H R/W Address: TMC00 FFFFF606H
6 5
<7>
OVFn CSn2 CSn1
OVFn
0 No overflow occurs
1
Overflow occurs
Preliminary User's Manual U15905EJ1V0UD
TMC10 FFFFF616H
4 3 2
CSn0 0 0
TMn register overflow detection
1
<0>
TMCEn TMCAEn
(1/2)
221