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15.8.2 Releasing backup mode
The backup mode can be released by inputting a high level to the RESET pin after restarting the power supplies
other than the backup power supply (V
When the backup mode has been released, the normal operation mode is set after the lapse of the oscillation
stabilization time.
Because the backup mode can be released only by the RESET signal, it must be checked if the data of the internal
RAM is valid or not, by using the BPSF bit of the backup power status register (BPS). The BPSF bit is set if a change
of voltage less than the data retention voltage on V
(including on power application), and cleared only by an instruction. This bit holds its value if a voltage greater than
the data retention voltage is supplied to V
V
.
DDBU
Therefore, it can be checked if the data of the internal RAM is valid or not by clearing the BPSF bit before the
backup mode is set, and checking the status of the BPSF bit by the reset processing routine after the backup mode
has been released. (If BPSF = 0, the data of the internal RAM is valid; if BPSF = 1, the data of the internal RAM is
invalid.)
The backup mode can be released using the following procedure.
<Releasing backup mode>
<1> Supply power other than backup power.
<2> When the power supply has been stabilized, clear the reset signal (input level 1 to the RESET pin), wait for
the oscillation stabilization time, and set the normal operation mode.
<3> Read the BPSF bit of the BPS register using the reset processing routine.
• BPSF = 0: The data of the internal RAM is valid (the data retention voltage is maintained on V
the period of the backup mode).
• BPSF = 1: The data of the internal RAM is invalid (if the voltage on V
voltage, or on power application).
Caution To release the backup mode, set V
• • • • V
= V
DDBU
DD
464
CHAPTER 15 STANDBY FUNCTION
and V
).
DDBU
SSBU
, and is not affected by a change of voltage on a power pin other than
DDBU
DDBU
= AV
= EV
= 2.2 V or more (f
DD
DD
Preliminary User's Manual U15905EJ1V0UD
or greater than the data retention voltage is detected
DDBU
DDBU
as follows, depending on the main clock frequency.
= 17 MHz)
XX
during
DDBU
drops below the data retention
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