Interrupt Control Register (Xxicn) - NEC V850E/IA1 mPD703116 User Manual

7.3.4 Interrupt control register (xxICn)

An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control
conditions for each maskable interrupt request.
This register can be read/written in 8-bit or 1-bit units.
Caution Read the xxIFn bit of the xxICn register in the interrupt disabled (DI) state. Otherwise if the
timing of interrupt acknowledgement and bit reading conflict, normal values may not be read.
<7> <6>
xxICn xxIFn xxMKn
Bit Position Bit Name
7 xxIFn
6 xxMKn
2 to 0 xxPRn2 to
xxPRn0
Remark xx: Identification name of each peripheral unit (refer to Table 7-2)
n: Peripheral unit number (refer to Table 7-2)
The address and bit of each interrupt control register are as follows.
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5 4 3
0 0 0
This is an interrupt request flag.
0: Interrupt request not issued
1: Interrupt request issued
The flag xxlFn is reset automatically by the hardware if an interrupt request is
acknowledged.
This is an interrupt mask flag.
0: Enables interrupt servicing
1: Disables interrupt servicing (pending)
8 levels of priority order are specified for each interrupt.
xxPRn2 xxPRn1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
User's Manual U14492EJ3V0UD
<2> <1> <0>
xxPRn2 xxPRn1 xxPRn0
Function
xxPRn0 Interrupt Priority Specification Bit
0 Specifies level 0 (highest).
1 Specifies level 1.
0 Specifies level 2.
1 Specifies level 3.
0 Specifies level 4.
1 Specifies level 5.
0 Specifies level 6.
1 Specifies level 7 (lowest).
Address Initial value
FFFFF110H to 47H
FFFFF176H
179