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15.7 Sub-IDLE Mode
15.7.1 Setting and operation status
The sub-IDLE mode is set when the PSM bit of the power save mode register (PSMR) is cleared to 0 and the STP
bit of the power save control register (PSC) is set to 1 in the subclock operation mode.
In this mode, the clock oscillator continues operation but clock supply to the CPU and the other on-chip peripheral
functions is stopped.
As a result, program execution is stopped and the contents of the internal RAM before the sub-IDLE mode was set
are retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral
functions that can operate with the subclock or an external clock continue operating.
Because the sub-IDLE mode stops operation of the CPU and other on-chip peripheral functions, it can reduce the
current consumption more than the subclock operation mode. If the sub-IDLE mode is set after the main clock has
been stopped, the current consumption can be reduced to a level as low as that in the software STOP mode.
Table 15-10 shows the operation status in the sub-IDLE mode.
15.7.2 Releasing sub-IDLE mode
The sub-IDLE mode is released by a non-maskable interrupt request (NMI pin input), unmasked external interrupt
request (INTP0 to INTP6 pin input), unmasked internal interrupt request from the peripheral functions operable in the
sub-IDLE mode, or RESET pin input.
When the sub-IDLE mode is released by an interrupt request, the subclock operation mode is set. If it is released
by RESET pin input, the normal operation mode is restored.
(1) Releasing sub-IDLE mode by non-maskable interrupt request or unmasked maskable interrupt request
The sub-IDLE mode is released by a non-maskable interrupt request or an unmasked maskable interrupt
request, regardless of the priority of the interrupt request. If the sub-IDLE mode is set in an interrupt servicing
routine, however, an interrupt request that is issued later is serviced as follows.
(a) If an interrupt request with a priority lower than that of the interrupt request currently being serviced is
issued, only the sub-IDLE mode is released, and that interrupt request is not acknowledged. The interrupt
request itself is retained.
(b) If an interrupt request with a priority higher than that of the interrupt request currently being serviced is
issued (including a non-maskable interrupt request), the sub-IDLE mode is released and that interrupt
request is acknowledged.
Table 15-9. Operation After Releasing Sub-IDLE Mode by Interrupt Request
Release Source
Non-maskable interrupt request
Maskable interrupt request
460
CHAPTER 15 STANDBY FUNCTION
Interrupt Enabled (EI) Status
Execution branches to the handler address
Execution branches to the handler
address or the next instruction is
executed
Preliminary User's Manual U15905EJ1V0UD
Interrupt Disabled (DI) Status
The next instruction is executed
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