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The CPU of the V850ES/SA2 and V850ES/SA3 is based on RISC architecture and executes almost all instructions
with one clock by using a 5-stage pipeline.
3.1
Features
Minimum instruction execution time: 58.9 ns (at 17 MHz operation: 2.2 V to 2.7 V)
Memory space
Program space: 64 MB linear
Data space:
• Memory block division function: 2, 2, 4, 8 MB/total: 4 blocks
General-purpose registers: 32 bits × 32 registers
Internal 32-bit architecture
5-stage pipeline control
Multiplication/division instruction
Saturation operation instruction
32-bit shift instruction: 1 clock
Load/store instruction with long/short format
Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
60
CHAPTER 3 CPU FUNCTION
30.5 ns (with subclock (f
4 GB linear
Preliminary User's Manual U15905EJ1V0UD
= 32.768 kHz operation))
XT
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