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5.7
Idle State Insertion Function
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus
cycle that is executed for each space selected by the chip select function in the multiplexed address/data bus mode.
In the separate bus mode, one idle state (TI) can be inserted after the T2 state. By inserting an idle state, the data
output float delay time of the memory can be secured during read access (an idle state cannot be inserted during
write access).
Whether the idle state is to be inserted can be programmed by using the bus cycle control register (BCC).
An idle state is inserted for all the areas immediately after system reset.
(1) Bus cycle control register (BCC)
This register can be read or written in 16-bit units.
Cautions 1. The internal ROM, internal RAM, and internal peripheral I/O areas are not subject to idle
state insertion.
2. Write to the BCC register after reset, and then do not change the set values. Also, do not
access an external memory area other than the one for this initialization routine until the
initial settings of the BCC register are complete. However, external memory areas whose
initial settings are complete may be accessed.
After reset:
BCC
CSn signal
Caution Be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0.
CHAPTER 5 BUS CONTROL FUNCTION
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R/W
Address:
15
14
13
1
0
1
7
6
5
BC31
0
BC21
CS3
CS2
Specifies insertion of idle state (n = 0 to 3)
BCn1
0
Not inserted
1
Inserted
Preliminary User's Manual U15905EJ1V0UD
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12
11
10
0
1
0
4
3
2
0
BC11
0
CS1
9
8
1
0
1
0
BC01
0
CS0
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