Table of Contents
Advertisement
16.3 Operation
The system is reset, initializing each hardware unit, when a low level is input to the RESET pin by WDT overflow
(WDTRES).
While a low level is being input to the RESET pin, the main clock oscillator stops. Therefore, the overall power
consumption of the system can be reduced.
If the RESET pin goes high or if WDTRES is received, the reset status is released.
If the reset status is released by RESET pin input, the oscillation stabilization time elapses (reset value of OSTS
19
register: 2
/f
) and then the CPU starts program execution.
X
If the reset status is released by WDTRES, the oscillation stabilization time is not inserted because the main
system clock oscillator does not stop.
Note Reset by WDT overflow (WDTRES) is valid only when the WDTM4 and WDTM3 bits of the watchdog timer
mode register (WDTM) are set to "11" (refer to 9.3 (3)).
468
CHAPTER 16 RESET FUNCTION
Preliminary User's Manual U15905EJ1V0UD
Advertisement
Table of Contents
