Control Registers - NEC V850ES/SA2 UPD703201 Manual

6.3

Control Registers

(1) Processor clock control register (PCC)
The processor clock control register (PCC) is a special register. Data can be written to it only in combination of
specific sequences (refer to 3.4.8 Special registers).
This register can be read or written in 8-bit or 1-bit units. The CLS bit is a read-only bit.
After reset:
PCC
Note The CLS bit is a read-only bit.
Caution Do not change the CPU clock (by using the CK2 to CK0 bits of the PCC register) while
CLKOUT is being output.
Remark X: Don't care.
208
CHAPTER 6 CLOCK GENERATION FUNCTION
03H R/W Address: FFFFF828H
<6>
FRC MCK MFRC
FRC Selects internal feedback resistor of subclock
0
Used
1
Not used
MCK
0 Operating
1 Stopped
• Even if the MCK bit is set to 1 while the system is operating with the main clock as
the CPU clock, the operation of the main system clock does not stop. It stops after
the CPU clock has been changed to the subclock.
• When the main clock is stopped and the device is operating on the subclock, clear
the MCK bit to 0 and wait until the oscillation stabilization time has been secured
by the program before switching back to the main clock.
MFRC Selects internal feedback resistor of main clock
0 Used
1
Not used
CLS
0
Main clock operation
1
Subclock operation
CK3 CK2 CK1
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
1 X X
Preliminary User's Manual U15905EJ1V0UD
<4> <3>
Note
CLS CK3 CK2
Operation of main clock
Status of CPU clock (f )
CPU
CK0 Selects clock
0 f
X
1 f /2
X
0 f /4
X
1 f /8
X
0 f /16
X
1
f /32
X
X
Setting prohibited
X
f (subclock: 32.768 kHz)
XT
CK1 CK0
(f /f )
XX CPU