Dma Byte Count Registers 0 To 3 (Dbc0 To Dbc3) - NEC V850ES/SA2 UPD703201 Manual

13.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3)

These 16-bit registers are used to set the byte transfer count for DMA channels n (n = 0 to 3). They store the
remaining transfer count during DMA transfer.
These registers can be read or written in 16-bit units.
Remark If the DBCn register is read during DMA transfer after a terminal count has occurred without the register
being overwritten, the value set immediately before the DMA transfer will be read out (0000H will not be
read, even if DMA transfer has ended).
After reset:
DBCn
(n = 0 to 3)
CHAPTER 13 DMA FUNCTIONS (DMA CONTROLLER)
Undefined R/W Address:
15 14 13
BC15 BC14 BC13
7 6 5
BC7 BC6 BC5
BC15 to Byte transfer count setting or remaining
BC0 byte transfer count during DMA transfer
0000H
Byte transfer count 1 or remaining byte transfer count
0001H
Byte transfer count 2 or remaining byte transfer count
:
:
FFFFH
Byte transfer count 65,536 (2
Preliminary User's Manual U15905EJ1V0UD
DBC0: FFFFF0C0H, DBC1: FFFFF0C2H,
DBC2: FFFFF0C4H, DBC3: FFFFF0C6H
12 11 10
BC12 BC11 BC10
4 3 2
BC4 BC3 BC2
16
) or remaining byte transfer count
9 8
BC9 BC8
1 0
BC1 BC0
407