Operation As External Event Counter (16 Bits) - NEC V850ES/SA2 UPD703201 Manual

7.3.6

Operation as external event counter (16 bits)

The V850ES/SA2 and V850ES/SA3 are provided with a 16-bit register that can be used only during cascade
connection.
The 16-bit resolution timer/event counter mode is selected by setting the TMC34 and TMC54 bits of 8-bit timer
mode control registers 3 and 5 (TMC3 and TMC5) to 1.
The external event counter counts the number of clock pulses input to the TI2 and TI4 pins from an external source
using 16-bit timer counters 23 and 45 (TM23 and TM45).
In the following description, TM2 and TM3 are used. Read TM2 and TM3 as TM4 and TM5 when using TM4 and
TM5.
Setting method (when TM2 and TM3 are connected in cascade)
<1> Set each register.
• TCL2 register:
• CR2 register:
• CR3 register:
• TMC2, TMC3 registers: Stops count operation, selects the clear & stop mode entered on a match
<2> Set the TCE3 bit of the TMC3 register to 1. Then set the TCE2 bit of the TMC2 register to 1 and count the
number of pulses input from TI2.
<3> When the values of the TM23 register and CR23 register connected in cascade match, INTTM2 is
generated (the TM23 register is cleared to 0000H).
<4> INTTM2 is then generated each time the values of the TM23 register and CR23 register match.
INTTM2 is generated when the valid edge of TI2 is input N + 1 times: N = 0000 to FFFFH
Cautions 1. During external event counter operation, do not rewrite the value of the CRn register.
2. To write using 8-bit access during cascade connection, set the TCE3 bit to 1 and then
set the TCE2 bit to 1. When operation is stopped, set the TCE2 bit to 0 and then set
the TCE3 bit to 0.
3. During cascade connection, TI2 input and INTTM2 input are used while TI3 input, TO3
output, and INTTM3 input are not, so set bits LVS3, LVR3, TMC31, and TOE3 to 0.
4. Do not change the value of the CR23 register during external counter operation.
260
CHAPTER 7 TIMER/COUNTER FUNCTION
Selects the TI2 input edge.
(The TCL3 register does not have to be set during cascade connection.)
Falling edge of TI2 → TCL2 = 00H
Rising edge of TI2 → TCL2 = 01H
Compare value (N) ... Lower 8 bits (settable from 00H to FFH)
Compare value (N) ... Higher 8 bits (settable from 00H to FFH)
between the TM23 register and CR23 register, disables timer output F/F
inversion, and disables timer output.
(×: don't care)
TMC2 register = 0000xx00B
TMC3 register = 0001xx00B
Preliminary User's Manual U15905EJ1V0UD