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2.2
Pin Status
The operating status of each pin in each operation mode is shown below.
Table 2-3. Operating Status of Each Pin in Each Operation Mode
Bus Control Pins
AD0 to AD15
A16 to A23
A0 to A8
WAIT
CLKOUT
CS0 to CS3
WR0, WR1
RD
ASTB
HLDAK
HLDRQ
Notes 1. Because the bus control pins function alternately as port pins, they are initialized to the input mode (port
mode).
2. Indicates the pin status in the idle state that is inserted after the T3 state.
Remark
Hi-Z:
High impedance
Retained: Status in external bus cycle immediately before is retained.
L:
Low-level output
H:
High-level output
−:
Input not sampled (not acknowledged)
CHAPTER 2 PIN FUNCTIONS
Reset
HALT Mode or
DMA Transfer
490
Hi-Z
Operates
Preliminary User's Manual U15905EJ1V0UD
IDLE and STOP
Idle State
Modes
Hi-Z
Retained
−
−
L
Operates
H
Retained
H
−
−
490
Bus Hold
Hi-Z
−
Operates
Hi-Z
L
Operates
43
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