Dma Transfer Count Registers 0 To 3 (Dbc0 To Dbc3) - NEC V850E/IA1 mPD703116 User Manual

32-bit single-chip microcontrollers

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6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)

These 16-bit registers are used to set the byte transfer counts for DMA channel n (n = 0 to 3). They store the

remaining transfer counts during DMA transfer.

Since these registers are 2-stage FIFO buffer registers, a new DMA byte transfer count for DMA transfer can be

specified during DMA transfer (refer to 6.9 Next Address Setting Function). In this case, if a new DBCn register is

set, the value set will be transferred to the slave register and enabled only if DMA transfer ends normally, and the TCn

bit of DMA channel control register n (DCHCn) has been set to 1 or the INITn bit of the DCHCn register has been set

to 1 (n = 0 to 3). However, take note that this value set will be disabled if the DBCn register is set with the Enn bit of

the DCHCn register cleared to 0 and DMA transfer prohibited.

These registers are decremented by 1 per transfer. Transfer is terminated if a borrow occurs.

These registers can be read/written in 16-bit units.

If the DBCn register is read after a terminal count has occurred during DMA transfer without the value of

the DBCn register being rewritten, the value set immediately before DMA transfer is read (0000H is not

read even after completion of transfer).

BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0

BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0

BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0

Bit Position

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)

Sets the byte transfer count. It stores the remaining byte transfer count during DMA

DBCn (n = 0 to 3)

User's Manual U14492EJ3V0UD

Byte transfer count 1 or remaining byte transfer count

Byte transfer count 2 or remaining byte transfer count

Byte transfer count 65,536 (2

Initial value

) or remaining byte transfer