Dma Byte Count Registers 0 To 3 (Dbc0 To Dbc3) - NEC V850E/MA1 User Manual

6.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3)

These 16-bit registers are used to set the byte transfer count for DMA channel n (n = 0 to 3). They store the
remaining transfer count during DMA transfer.
Since these registers are configured as 2-stage FIFO buffer registers, a new DMA byte transfer count for DMA
transfer can be specified during DMA transfer. (Refer to 6.9 Next Address Setting Function.)
These registers are decremented by 1 for each transfer, and transfer ends when a borrow occurs.
These registers can be read/written in 16-bit units.
Remark If the DBCn register is read during DMA transfer after a terminal count has occurred without the
register being overwritten, the value set immediately before the DMA transfer will be read out (0000H
will not be read, even if DMA transfer has ended).
15 14 13 12
DBC0 BC15 BC14 BC13 BC12
DBC1 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
DBC2 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
DBC3 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
Bit position Bit name
15 to 0 BC15 to BC0
212
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
11 10 9 8 7 6
BC11 BC10 BC9 BC8 BC7 BC6
Byte Count
Sets the byte transfer count and stores the remaining byte transfer count during
DMA transfer.
DBCn (n = 0 to 3)
0000H
0001H
:
FFFFH
User's Manual U14359EJ4V0UM
5 4 3 2 1 0
BC5 BC4 BC3 BC2 BC1 BC0
Function
States
Byte transfer count 1 or remaining byte transfer count
Byte transfer count 2 or remaining byte transfer count
:
16
Byte transfer count 65,536 (2
count
Address After reset
FFFFF0C0H Undefined
FFFFF0C2H Undefined
FFFFF0C4H Undefined
FFFFF0C6H Undefined
) or remaining byte transfer