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4.17.2 PMC1 Site Features
• PMC1 shares PCI Bus 1 with the cPCI backplane interface (PCI 6254 cPCI Bridge), the
USB 2.0 Host controller interface through the PCI2050B PCI/PCI Bridge, and the
GD31244 SATA Host Controller.
• PCI Bus 1 supports 64-bit 33/66MHz operation.
NOTE: PCI Bus 1 will operate at 66MHz if a PMC module supporting 66MHz operation
is installed. If the installed PMC module only supports 33MHz operation, PCI Bus 1 will
revert to 33MHz operation. This will impact I/O transfer rates to and from the cPCI back-
plane but not backplane transfer rates between other boards.
• VIO for PCI Bus 1 is configurable to either +5V or +3.3V through PCI Bus 1 VIO Select
jumper (J9) (see "PCI VIO Select (P9, P12)" on page 2-2).
NOTE: Setting PCI Bus 1 VIO to +5V forces the bus speed to 33MHz.
• PMC1_P24 is routed to cPCI_J5 using PICMG 2.3 wiring definitions. It also supports the
differential signal PCB trace requirements defined for Sentiris S4110 PMC LVDS interface
and G2 PMC.
• PMC1 is intended for lower capacity I/O and may host a PMC with power rating of 7.5W
or lower, if the module on PMC0 is 7.5W or less. PMC 1 can host a 15W PMC module if
no PMC module is installed on PMC0.
NOTE: Combined power dissipation for both PMC sites cannot exceed 15W.
4.18 Temperature Sensor
The C2K includes a MAX6658 Dual Channel Temperature Sensor that monitors the MPC7448
processor temperature through an on-die thermal diode and board temperature with an on-chip
sensor. The Temperature Sensor is attached to the MV64460 Bridge chip through the I2C SMBus
at address 0x4C.
Boot code must program the temperature sensor to generate an over-temperature alarm if the CPU
die reaches 102ºC or if the ambient temperature exceeds 85ºC. The over-temperature alarm will
initiate a hard-reset of the board, holding the board in reset until the alarm condition clears. The
default, power-up, values are:
• Generate interrupt at -55 ºC or below or +70ºC and above
• Generate over-temperature alarm at +85ºC or above
The over-temperature alarm is ignored unless the OVRTEMP_RST_EN bit (bit 15) in the FPGA
Control Register (see "Control Register" on page 5-9) is set. This avoids resetting the C2K prior
to the CPU reprogramming the sense thresholds.
4.19 Interrupt Circuitry
The C2K uses the FPGA Interrupt Summary registers (see "Interrupt Registers" on page 5-11), to
capture external (cPCI and PMC) interrupts and board interrupts as shown in Figure 4-3. When
one of these interrupts is asserted, the FPGA asserts an interrupt to the MV64460 System
Controller MPP port. In addition to the FPGA interrupt, the Ethernet PHY interrupt, the
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Functional Blocks
C2K User's Guide
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