GE C2K Hardware Reference Manual page 80

Bits Field
7 IPMC_INT_STAT
6 8051_UART_INT_STAT
5 USART_INT5_STAT
4 USART_INT4_STAT
3 USART_INT3_STAT
2 USART_INT2_STAT
1 USART_INT1_STAT
0 USART_INT0_STAT
SMI Mask Register
The SMI Mask Register provides masking for signals that are capable of triggering the CPU
SMI# input to the processor.
Address offset: 0x28
Access: Read/write
Bits Field
15 to 4 Not used
3 DEG_MSK
2 FAL_MSK
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Default
- IPMC Interrupt Status—indicates the status of the IPMC
interrupt.
0 = interrupt is de-asserted
1 = interrupt is asserted
- 8051 UART Interrupt Status—indicates the status of the
8051 UART interrupt.
0 = interrupt is de-asserted
1 = interrupt is asserted
- USART INT5 Status—indicates the status of the USART
Port 5 interrupt.
0 = interrupt is de-asserted
1 = interrupt is asserted
- USART INT4 Status—indicates the status of the USART
Port 4 interrupt.
0 = interrupt is de-asserted
1 = interrupt is asserted
- USART INT3 Status—indicates the status of the USART
Port 3 interrupt.
0 = interrupt is de-asserted
1 = interrupt is asserted
- USART INT2 Status—indicates the status of the USART
Port 2 interrupt.
0 = interrupt is de-asserted
1 = interrupt is asserted
- USART INT1 Status—indicates the status of the USART
Port 1 interrupt.
0 = interrupt is de-asserted
1 = interrupt is asserted
- USART INT0 Status—indicates the status of the USART
Port 0 interrupt.
0 = interrupt is de-asserted
1 = interrupt is asserted
Default
- Not used
1 DEG# signal Mask—blocks (masks) the backplane
DEG# signal from asserting the CPU_SMI#.
0 = enable DEG# signal
1 = disable (mask) DEG# signal
1 FAL# signal Mask—blocks (masks) the backplane FAL#
signal from asserting the CPU_SMI#.
0 = enable FAL# signal
1 = disable (mask) FAL# signal
Resources
Description
Description
5-14