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Bit(s)
Field
0
DR
USART Modem Status Register
The USART Modem Status Register provides access to status indicators on the USART modem
interface.
Address offset:
USART_Base +0x6
Access:
Read-only
Bit(s)
Field
7
DCD
6
RI
5
DSR
4
CTS
3
DDCD
2
TERI
1
DDSR
0
DCTS
USART Scratchpad Register
The USART Scratchpad Register provides an open register for scratchpad data or test purposes.
Writes have no impact on USART operation. When the USART is configured for extended FIFO
≠
size (
FIFO size 0b00
) and FIFO mode is enabled, the USART Scratchpad Register provides a
secondary function—it indicates the actual number of bytes in the Receive FIFO when a time-out
interrupt is generated.
Address offset:
USART_Base +0x7
Access:
Read/write
Bit(s)
Field
7 - 0
SCRATCH
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Default
0
Data Ready—indicates that an incoming character has been received
and transferred to the Receive Data buffer or Receive FIFO. This bit is
cleared on a read from the Receive Buffer Register or when the FIFO is
empty.
0 = no incoming data has been received
1 = incoming data has been received
Default
0
Compliment of external DCD input—equals OUT2 in loopback mode.
0
Compliment of external RI input—equals OUT1 in loopback mode.
0
Compliment of DSR input—equals DTR in loopback mode.
0
Compliment of external CTS input—equals RTS in loopback mode.
0
Delta Data Carrier Detect—indicates a change of state on DCD line.
0 = no change of state
1 = change of state on DCD line
0
Trailing Edge of Ring Indicator—indicates a change of state from low to
high on the RI line.
0 = no change of state
1 = change of state from low to high on RI line
0
Delta Data Set Ready—indicates a change of state on the DSR line.
0 = no change of state
1 = change of state on DSR line
0
Delta Clear To Send—indicates a change of state on the CTS line.
0 = no change of state
1 = change of state on CTS line
Default
0x00
Scratchpad data—number of bytes in the Receive FIFO
Description
Description
Description
Resources
5-52
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