GE C2K Hardware Reference Manual page 117

USART Line Status Register
The USART Line Status Register provides access to status indicators on the UART line interface.
Address offset: USART_Base +0x5
Access: Read-only
Bit(s) Field
7 ERR_INF
6 TEMPT
5 THRE
4 BI
3 FE
2 PE
1 OE
5-51
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Default
0 Error in FIFO—this bit is always cleared in Register mode. In FIFO
mode, this bit indicates that at least one parity error, framing error, or
break indication has been received and is inside the Receive FIFO
buffer. The ERR_INF bit is cleared on a read if no other errors reside in
the FIFO buffer.
0 = no error in FIFO has occurred
1 = error in FIFO has occurred
1 Transmitter Empty—indicates when both the Transmit Holding Register
and the Transmit Shift Register are empty. In FIFO mode, this bit indi-
cates that both the Transmit FIFO and Transmit Shift Register are
empty.
0 = transmitter is not empty
1 = transmitter is empty
1 Transmit Holding Register Empty—indicates that the Transmit Holding
Register is ready to accept a new character. In FIFO mode, this bit indi-
cates the entire transmit FIFO buffer is empty.
0 = Transmit Holding Register is not empty
1 = Transmit Holding Register is empty
0 Break Indicator—indicates when the receive data is held at logic (0) for
at least one full character (start bit + data + parity + stop bit) time. In
FIFO mode, this applies to the character at the top of the FIFO buffer.
This bit also generates a Receiver Line Status interrupt. The Break Indi-
cator bit is cleared when read.
0 = no break event has occurred
1 = break event has occurred
0 Framing Error—indicates when a received character does not have a
valid stop bit. In FIFO mode, this applies to the character at the top of
the FIFO buffer. This bit also generates a Receiver Line Status inter-
rupt. The Framing Error bit is cleared when read.
0 = no framing error has occurred
1 = framing error has occurred
0 Parity Error—indicates the received character has incorrect parity. In
FIFO mode, this applies to the character at the top of the FIFO buffer.
This bit also generates a Receiver Line Status interrupt. The Parity
Error bit is cleared when read.
0 = no parity error has occurred
1 = parity error has occurred
0 Overrun Error—indicates when a new receive character is transferred
to the Transmit Holding Register before the prior character was read, or
that the FIFO buffer is full and a complete new character is received in
the Shift Register. This bit also generates a Receiver Line Status inter-
rupt. The Overrun Error bit is cleared when read.
0 = no overrun error has occurred
1 = overrun error has occurred
Description
C2K User's Guide
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