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Bits
Field
1
WDOG_NMI_MSK
0
GPIO_NMI_MSK
SMI Status
The SMI Status Register provides status information for signals capable of triggering the
CPI_SMI# input to the processor.
Address offset:
0x2A
Access:
Read/write
Bits
Field
15 to 4
Not used
3
DEG_STAT
2
FAL_STAT
1
WDOG_NMI_STAT
0
GPIO_NMI_STAT
5-15
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Default
1
Watchdog NMI Mask—blocks (masks) the MV64460
Watchdog NMI signal from asserting the CPU_SMI# (NMI
is signaled through the SMI# input).
0 = enable WDOG NMI signal
1 = disable (mask) WDOG NMI signal
1
NMI on GPIO15 Interrupt Mask—blocks (masks) the NMI
signal on the GPIO15 line.
0 = enable SMI
1 = disable (mask) SMI
Default
-
Not used
1
DEG# signal Status—indicates the backplane DEG# sig-
nal status.
0 = DEG# signal is de-asserted
1 = DEG# signal is asserted
1
FAL# signal Status—indicates the backplane FAL# signal
status.
0 = FAL# signal is de-asserted
1 = FAL# signal is asserted
1
Watchdog NMI Status—indicates the MV64460 Watch-
dog NMI signal status.
0 = WDOG NMI signal is de-asserted
1 = WDOG NMI signal is asserted
1
NMI on GPIO15 Input Active (if enabled)—indicates the
NMI signal is active on the GPIO15 line.
0 = input inactive
1 = input active
Resources
Description
Description
C2K User's Guide
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