GE C2K Hardware Reference Manual page 107

Bits Field
2 CNTR2_MODE
1 CNTR1_MODE
0 CNTR0_MODE
Counter Interrupt Mask Register
The Counter Interrupt Mask provides interrupt masking for each counter.
Address offset: 0x56
Access: Read/write
Bits Field
15 CNTR15_INT_MSK
14 CNTR14_INT_MSK
13 CNTR13_INT_MSK
12 CNTR12_INT_MSK
11 CNTR11_INT_MSK
10 CNTR10_INT_MSK
9 CNTR9_INT_MSK
8 CNTR8_INT_MSK
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Default
0 Counter 2 Mode—configures counter 2 as a timer or counter.
0 = counter
1 = timer
0 Counter 1 Mode—configures counter 1 as a timer or counter.
0 = counter
1 = timer
0 Counter 0 Mode—configures counter 0 as a timer or counter.
0 = counter
1 = timer
Default
1 Counter 15 Interrupt Mask—blocks (masks) the interrupt for
counter 15.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 14 Interrupt Mask—blocks (masks) the interrupt for
counter 14.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 13 Interrupt Mask—blocks (masks) the interrupt for
counter 13.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 12 Interrupt Mask—blocks (masks) the interrupt for
counter 12.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 11 Interrupt Mask—blocks (masks) the interrupt for
counter 11.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 10 Interrupt Mask—blocks (masks) the interrupt for
counter 10.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 9 Interrupt Mask—blocks (masks) the interrupt for
counter 9.
0 = enable interrupt
1 = disable (mask) interrupt
1 Counter 8 Interrupt Mask—blocks (masks) the interrupt for
counter 8.
0 = enable interrupt
1 = disable (mask) interrupt
Description
Description
C2K User's Guide
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