Table 4-5 I/O Controller Pin Assignments - GE C2K Hardware Reference Manual

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Table 4-5 lists the I/O controller pin assignments.
I/O controller pin assignments
Table 4-5
Pin
IO1 Assignments
9
SRAM A16
8
ICMB_ARB_CTL
7
ICMB_ARB_SEL
6
SYSEN#
5
BDSEL#
4
GA4
3
GA3
2
GA2
1
GA1
0
GA0
NOTES:
a.
The PCI_PRESENT# input does not directly affect the C2K operation. The Hot-Swap function operates as
normal, whether the backplane PCI_PRESENT# signal is asserted or not.
b.
The ALERT# input is an optional signal used to support legacy IPMI devices. This signal is made available to
the IPMC, should the feature be demanded. A pull-up on the C2K ensures this signal remains in the negated
state, if unused.
c.
The SYSEN#, BDSEL#, and GA4-0 inputs are monitored, and used as described in PICMG 2.9, PICMG 2.1,
and PICMG 2.0. BDSEL# may be driven by the C8051 under certain conditions.
d.
The PWRGOOD monitor inputs, PGOOD_V12, PGOOD_V125, PGOOD_V15, PGOOD_V25_V11 are all
active-high power-good indications from the on-board regulators. The HSC_PWRGOOD# input is the HSC
active-low power-good indication that represents valid power for on-board +5V, +3.3V, and +12V supplies.
e.
BRD_RST# is an open-drain output with an external pull-up that is used to initiate a board reset. The C2K is
held in reset while this signal is active.
IIC Bus
The HSC uses the IIC Bus to generate the Hot Swap-compliant IPMB0 Bus.
Serial Interface
The internal UART1 must be connected to Port 1 through the crossbar to provide a serial interface
for in-system programming and other messaging between the MPC7448 processor and the C8051
Controller. This serial interface is connected to the FPGA UART #8.
Analog Compare Inputs
The CP0+/- and CP1+/- inputs are intended to works as digital input monitors. CP1 is attached to
the M66EN_COS# signal from the CPLD. When a change of M66EN state is encountered during
operation, the IMPC issues an orderly shutdown and reboot of the C2K
monitors the ICMB receive data, to support the ICMB arbitration feature.
D/A Outputs
The C8051 Controller provides two digital-to-analog converter outputs. The C2K does not use
these outputs.
4-13
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IO2 Assignments
PGOOD_1.2V
PGOOD_1.25V
PGOOD_1.5V
PGOOD_2.5V / 1.1V
HSC_PWRGOOD#
FPGA_INT#
BRD_RESET#
YELLOW_LED
UART_RST#
SMB_ALERT#
Functional Blocks
The CP0+/- input
.
C2K User's Guide

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