Table of Contents
Advertisement
USART Transmit Buffer Register
The USART Transmit Buffer Register holds the data to be transmitted. Its contents are automati-
cally transferred to the outgoing shift register. In FIFO mode, writes to this register are pushed to
the bottom of the memory buffer.
Address offset:
USART_Base +0x0
DLAB:
0
Access:
Write-only
Bits
Field
7 - 0
TXDATA
USART Interrupt Enable Register
The USART Interrupt Enable Register provides a mechanism to enable individual causes to gen-
erate an external USART interrupt.
Address offset:
USART_Base +0x1
Access:
Read/write
Bit(s)
Field
7 - 4
Not used
3
Modem
2
Line
1
TX
0
RX
USART Interrupt Identification Register
The USART Interrupt Identification Register provides the status and source of the pending
USART interrupt with the highest priority.
Address offset:
USART_Base +0x2
Access:
Read-only
Bit(s)
Field
7 - 6
FIFO
5 - 4
Not used
5-47
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
Default
-
Transmit buffer data
Default
-
Not used
0
Modem Status Interrupt Enable—enables the modem status interrupt.
0 = block (mask) interrupt cause
1 = enable interrupt cause
0
Received Line Status Interrupt Enable—enables an interrupt indicating
the received line is available.
0 = block (mask) interrupt cause
1 = enable interrupt cause
0
Transmit Holding Register Interrupt Enable—enables an interrupt indi-
cating the Transmit Holding Register is empty.
0 = block (mask) interrupt cause
1 = enable interrupt cause
0
Receive Data Interrupt Enable—enables an interrupt indicating receive
data is available.
0 = block (mask) interrupt cause
1 = enable interrupt cause
Default
0b00
FIFO Buffer status—indicates the status of the FIFO buffer.
0b11 = FIFO mode is enabled
-
Not used
Description
Description
Description
C2K User's Guide
Resources
Advertisement
Table of Contents
