GE C2K Hardware Reference Manual page 114

Bit(s) Field
3 - 1 ID
0 NPEND
The USART clears the various interrupt indications in different ways depending on the source of
the interrupt as listed below:
Receiver Line Status interrupt:
Receiver Data Available interrupt:
FIFO buffer falls below the trigger level.
cleared by reading from the FIFO buffer.
Time-out interrupt:
Transmit Holding Register Empty interrupt:
Register when it is the source of the interrupt, or by writing to the Transmit Data Register.
Modem Status interrupt:
Identification Register
USART FIFO Control Register
The USART FIFO Control Register enables and clears the transmit and receive data FIFO buffers
and sets the trigger levels.
Address offset: USART_Base +0x2
Access: Write-only
Bit(s) Field
7 - 6 RX_TRIG
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Default
0b000 Interrupt Identification as highest priority—identifies the interrupt with
highest priority.
0b011 (1st) = receiver line status
0b010 (2nd) = receiver data available
0b001 (3rd) = Transmit Holding Register empty
0b000 (4th) = modem status
1 Interrupt Pending—indicates an USART interrupt is pending.
0 = interrupt is pending
1 = no interrupt is pending
cleared by reading the Line Status Register.
cleared by reading the Receive Buffer Register or when the
cleared either by reading the Interrupt Identification
cleared by reading the Modem Status Register.
Default
0b00 Receive FIFO Trigger Level—sets the Receive FIFO buffer trigger
levels.
16-byte FIFO –
0b00 = 1 byte
0b01 = 4 bytes
0b10 = 8 bytes
0b11 = 14 bytes
256-byte FIFO –
0b00 = 1 byte
0b01 = 32 bytes
0b10 = 64 bytes
0b11 = 128 bytes
Description
Description
64-byte FIFO –
0b00 = 1 byte
0b01 = 16 bytes
0b10 = 32 bytes
0b11 = 56 bytes
1024-byte FIFO –
0b00 = 1 byte
0b01 = 64 bytes
0b10 = 128 bytes
0b11 = 256 bytes
Resources
5-48