Usart Registers; Table 5-11 Usart Resister - GE C2K Hardware Reference Manual

5.2.5 USART Registers

The FPGA provides six synchronous/asynchronous transmitter/receiver ports. Each operates
independently, supporting transmit enable, transmit data, transmit clock, receive data, and receive
clock. The ports each can be configured to operate as standard asynchronous character oriented
UARTs, or as USARTs. As a USART, the receive data must be aligned to the receive clock. The
transmit data is aligned to the transmit clock. The transmit clock may be sourced from the internal
baud-rate-generator for that specific port, or may be sourced from the port's receive clock.
NOTE: Standard 16550 DMA features are not provided
Table 5-11 lists the USART Registers.
USART Resister
Table 5-11
Offset Register
0xF0 USART 0 Control/Mode
0xF2 USART 1 Control/Mode
0xF4 USART 2 Control/Mode
0xF6 USART 3 Control/Mode
0xF8 USART 4Control/Mode
0xFA USART 5 Control/Mode
0xFC Unused
0xFE Unused
USART Control/Mode Register
The USART Control/Mode Register sets the extended configuration parameters for the USART
ports.
Address offset: 0xF0–0xFE
Access: Read/write
Bits Field
15 - 8 Not used
7 ACTIVATE
6 Not used
5 TEST_FE
4 TEST_PE
5-45
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Description
Default
- Not used
0 Logical Device Activation—enables the logical device.
0 = disable
1 = enable
- Not used
0 Framing Error Test Mode—truncates transmitted stop bit
to one-half bit time in asynchronous mode; stop bit is
omitted completely in synchronous mode.
0 = stop bit is not altered
1 = stop bit is truncated/omitted
NOTE:
This bit must be cleared (0) for normal operation.
0 Parity Error Test Mode—inverts transmitted parity bit.
0 = parity bit non-inverted
1 = parity bit inverted
NOTE:
This bit must be cleared (0) for normal operation.
Resources
Description
C2K User's Guide