Boot Code Selection; Pci Busses - GE C2K Hardware Reference Manual

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Boot Area Write-Protect Notes:

When the boot area write-protect is enabled, the user area can still be modified.

The flash ROM must be mapped to an even 8MB boundary for the boot area write-protect to work correctly.

Since the flash ROM device erase command is issued at address 0x0, a device erase will erase the boot area.

4.3.2 Boot Code Selection

Flash memory is segmented into two sections: emergency boot code area (upper 8MB of flash)

and user boot code area (remaining memory space). GEIP provides emergency boot code that is

stored in the emergency boot code area. Application developers can store custom boot code or

other custom software in the user boot code area.

Selection of which boot code is used to boot the C2K is controlled through the EM_BOOT_SEL

bit (bit 6) in the FPGA Status Register (see "Status Register" on page 5-8). Upon power-up or

after a hard reset, the GEIP-provided firmware will check the EM_BOOT_SEL bit to determine

which boot code area to execute boot code from. When the EM_BOOT_SEL bit is cleared, the

processor will jump to the user boot code area and boot up using the code stored in that area,

provided that a boot description header with a valid checksum is detected. If the bit is set, the

processor will continue to execute boot code from the emergency boot code area.

The EM_BOOTSEL# signal controls the setting of the EM_BOOT_SEL bit. The C2K provides

two methods for asserting (driving low) the EM_BOOTSEL# signal: an 2-pin on-board

header/jumper site (P7) (see "EM_BOOTSEL# (P7)" on page 2-2), or an external jumper (see

Note b. below) attached to a backplane connector pin (cPCI_J5 B9).

Boot Code Selection Notes:

A jumper is not typically installed on P7, however a jumper will need to be installed on P7 for initial power-up.

GEIP offers an optional C2K-TM companion board that provides a EM_BOOTSEL# header/jumper for

asserting the backplane EM_BOOTSEL# signal.

The C2K includes two PCI busses controlled by the MV64460 System Controller's PCI Bus

interface:

PCI Bus 0 is configured for 64-bit 33/66MHz PCI or 133MHz PCI-X operation and is dedicated

to the PMC0 site.

PCI Bus 1 is configured for 64-bit 33/66MHz PCI 2.2 and is shared by PMC1 site, the USB 2.0

Controller through the PCI2050B PCI/PCI Bridge, the GD31244 Serial ATA Controller, and the

PCI 6254 cPCI Bridge.

Both PCI busses can be configured for +3.3V or +5V VIO through on-board 3-pin PCI VIO

Configuration jumpers P12 for PCI Bus 0 and P9 for PCI Bus 1

NOTE: Each PCI Bus is limited to 33MHz PCI when configured for +5V VIO.

4-3

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C2K User's Guide

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