Cpld Control And Status Registers; Cpld Description; Figure 3-1 Block Diagram For Cpld - GE OpenVPX VPXcel6 SBC622 Hardware Reference Manual

3 • CPLD Control and Status Registers

3.1 CPLD Description

Figure 3-1 Block Diagram for CPLD

LFRAME#
LAD[3..0]
PCI CLK
RESET#
GE's SBC622 features additional capabilities beyond those of a typical desktop
computer system. The units provide two software‐controlled, general‐purpose
timers along with a programmable Watchdog Timer for synchronizing and
controlling multiple events in embedded applications. The SBC622 provides a
bootable NAND Flash system and 512 KBits of non‐volatile SEEPROM.
The SBC622 CPLD provides a general purpose I/O port, Watchdog Timer, and
general purpose timers. The block diagram for the CPLD is shown in the figure
below.
IO addr: 0x600+
RT
LPC
Interface
IO addr: 0x640+
GPIO
LPC
Interface
The CPLD contains two LPC interfaces; the RT suite LPC interface and the 8‐bit
GPIO port LPC interface.
32-bit Timer
32-bit Timer
WDT
Board ID
BMM Ctrl. Reg.
Serial Ctrl. Reg.
GPIO

CPLD Control and Status Registers 49