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VMEchip2
2
Reset Driver
Local Bus Interrupter and Interrupt Handler
2-18
In addition to the VMEbus timer, the chip contains a local bus timer. This
timer asserts the local TEA when the local bus cycle maintained in its
asserted state for longer that the programmed time-out period. This timer
can be enabled or disabled under software control. The time-out period can
be programmed for 8, 64, or 256 secs.
The chip includes both a global and a local reset driver. When the chip
operates as the VMEbus system controller, the reset driver provides a
global system reset by asserting the VMEbus signal SYSRESET. A
SYSRESET may be generated by the
watch dog time-out, or by a control bit in the LCSR. SYSRESET remains
asserted for at least 200 msec, as required by the VMEbus specification.
Similarly, the chip provides an input signal and a control bit to initiate a
local reset operation.
The local reset driver is enabled even when the chip is not the system
controller. A local reset may be generated by the
up reset, a watch dog time-out, a VMEbus SYSRESET, or a control bit in
the GCSR.
There are 31 interrupt sources in the VMEchip2: VMEbus ACFAIL,
switch, VMEbus SYSFAIL, write post bus error, external input,
ABORT
VMEbus IRQ1 edge-sensitive, VMEchip2 VMEbus interrupter
acknowledge, tick timer 2-1, DMAC done, GCSR SIG3-0, GCSR location
monitor 1-0, software interrupts 7-0, and VMEbus IRQ7-1. Each of the 31
interrupts can be enabled to generate a local bus interrupt at any level. For
example, VMEbus IRQ5 can be programmed to generate a level 2 local
bus interrupt.
The VMEbus AC fail interrupter is an edge-sensitive interrupter connected
to the VMEbus ACFAIL signal line. This interrupter is filtered to remove
the ACFAIL glitch which is related to the BBSY glitch.
The SYS fail interrupter is an edge-sensitive interrupter connected to the
VMEbus SYSFAIL signal line.
switch, a power up reset, a
RESET
RESET
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switch, a power
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