Programming The Programmable Clock - Motorola MVME172 Programmer's Reference Manual

Programming the Programmable Clock

Programmable clock registers are defined in the following paragraphs.
The registers which control IP_c and IP_d are not used on the 200/300-
Series MVME172.
programmable Clock Interrupt Control Register
ADR/SIZ
BIT
7
NAME
0
OPER R
RESET
0 R
IL2-0
ICLR
IEN
INT
IRE
http://www.mcg.mot.com/literature
$FFFBC080 (8 bits)
6 5 4
IRE INT IEN
R/W R R/W
0 R 0 R 0 R
These three bits select the interrupt level for the
programmable clock interrupt. Level 0 does not generate
an interrupt.
Writing a logic 1 to this bit clears the INT status bit. This
bit always reads as 0.
When IEN is set, the programmable clock interrupt is
enabled. When IEN is cleared, the interrupt is disabled.
When this bit is high, an interrupt is being generated for
the programmable clock at the level programmed in IL2-
IL0.
This bit controls which action of the programmable clock
output causes interrupts.
Programmable Clock Action
IRE
0
1
Programming Model
3 2
ICLR IL2
C R/W
0 R 0 R
That Causes Interrupts
Rising Edge
Falling Edge
1 0
IL1 IL0
R/W R/W
0 R 0 R
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