Reset
2.7 Reset
Logic is provided on the DSP56F801 to generate a clean Power-On RESET signal.
Additional, reset logic is provided to support the RESET signals from the JTAG
connector, the Parallel JTAG Interface and the user RESET push-button; refer to
Figure
2-6.
+3.3V
RESET
PUSHBUTTON
MANUAL RESET
RESET
P_RESET
Figure 2-6. Block Diagram of the RESET Interface
Technical Summary
2-9